The growing size of applications, popularity of software-based multimedia, and increasing graphics workloads have contributed to an increased demand in memory capacity. Many computer systems, such as servers, workstations, networking equipment, and high-end desktop computers, are often configured with only enough memory to support applications of the day and are not typically configured with enough memory to support applications that may be run on the same system in the future. FIG. 1 shows an isometric view of memory 102 and processor 104 components disposed on a motherboard 106 of a computer system configured to support a DDR interface. The memory 102 is composed of four dual in-line memory modules (“DIMMs”) 108-111 inserted into four DIMM slots 112-115, respectively. Each DIMM includes eight dynamic random access memory (“DRAM”) chips. The processor 104 is a chip that manages the flow of data sent to and from the DIMMs 108-111 and interfaces the memory 102 with other major components of the computer system. The DIMMs 108-111 are in electrical communication with the processor 104 via a DDR interface 118 which has a stub-bus topology providing a shared, parallel-path interface for sending data, address, and control information in electronic signals in parallel between the processor 104 and the data lines of every DRAM in the DIMMs 108-111.
The term “DDR” refers to transmitting data on both the rising and falling edges of the computer system clock signal. The processor 104 and the DIMMs 108-111 are configured to transmit and receive data in accordance with DDR. By using both edges of the clock, the data signals operate at the same limiting frequency, doubling the data transmission rate. There are a number of different DDR interface 118 implementations that are identified in general by DDRx, where x is a whole number. For example, DDR1 employs double-data-rate signalling on the data lines, but the address and control signals are still sent to the DIMMs once per clock cycle period. DDR2 operates at twice the speed of DDR1, which is accomplished by operating the memory cells of each DRAM at half the clock rate rather than at the clock rate as in DDR1. DDR3 provides the ability to run the input/output bus at four times the speed of the memory cells.
In order to keep pace with the ever increasing memory demands that new applications, or new application versions, place on a computer system, a computer system operator can increase the memory of the computer system by simply adding DIMMs to existing DDR memory channels and switch to a buffered memory design. However, when DIMMs are added to electrical DDR memory channels, electrical loading causes bus timing errors which persist until the bus speed is reduced. As a result, a tradeoff exists between maximum memory size and maximum memory speed. Alternatively, with buffered memory designs, power and latency are always incurred, whether or not the memory is fully loaded. Because once a few DIMMs can be loaded per buffered channel, even the buffered systems are limited in the memory that can be provisioned. In addition, each added buffer adds power consumption and cost, making this solution undesirable for high volume, low-cost systems.
Other factors to consider in simply adding DIMMs to a computer system are that conventional processors utilize two types of on-board memory controllers: 1) buffered memory and 2) direct-attached memory. A memory controller is a digital circuit that manages the flow of data to and from the DIMMs and can be implemented as a separate chip or integrated within a chip, such as a processor. Memory controllers contain the logic necessary to read and write DRAM and to refresh the DRAM by sending current through the entire device. Buffered memory systems allow a mechanism for memory expansion and always incur the cost of the buffers whether or not the memory is fully populated. On the other hand, direct-attached memory allows for low-cost implementations and uses less power than buffered memory, because direct-attached memory does not require buffer chips, but direct-attached memory is inherently limited by electrical loading effects. As a result, direct-attached memory systems are limited in the amount of memory that can be controlled and used by a single processor. Thus, in order to add more memory to a server or multi-processor system, more processors are added.
What is desired is a system that allows memory expansion and disaggregation of the memory so that DRAM memory can be increased when needed without the relatively higher cost associated with having to redesign and build a new computer system to support the increasing memory demands of the latest applications.